1. Field of the Invention
The present invention relates to semiconductor devices.
2. Description of the Related Art
In recent years, it has been proposed that CMOS transistor circuits are used for high-frequency power amplifiers in transmission section of portable wireless terminals (see JP-A 2007-60616 (KOKAI)). CMOS transistors used for the integrated circuits are produced by micro-processes and thus have low breakdown voltage. Thus, large current conduction is necessary in order to output high power. To obtain large output current, a structure has been proposed in which a plurality of transistors are arranged in the same device region and connected together in parallel. In this case, a layout configuration called a multi-finger structure is widely used. In the multi-finger layout structure, a plurality of gate electrodes arranged parallel to one another and electrically connected together are arranged on the same device region.
However, in an amplification circuit using CMOS transistors with the multi-finger layout structure, the amplitude exhibiting linearity between an input signal and an output signal is limited. Thus, with this layout structure, providing a high-performance power amplifier with high linearity has conventionally been difficult.